1. Field of the Invention
The present invention relates to a spatial light modulator (SLM) implemented with a mirror device for modulating incident light to project images for an image display system. More particularly, this invention relates to a mirror device with structure to connect an elastic hinge supporting the mirror.
2. Description of the Related Art
Even though there are significant advances of the technologies for implementing an electromechanical mirror device as a spatial light modulator (SLM) in recent years, there are still limitations and difficulties when it is employed to display a high quality image. Specifically, when the images are digitally controlled, the image quality is adversely affected due to the fact that the images are not displayed with sufficient number of gray scales.
An electromechanical mirror device is drawing a considerable interest as a spatial light modulator (SLM). The electromechanical mirror device consists of a “mirror array” implemented with a large number of mirror elements. In general, the mirror array may include from 60,000 to several millions of mirror elements arranged on a surface of a substrate in an electromechanical mirror device.
Referring to FIG. 1A, an image display system 1 including a screen 2 is disclosed in a reference U.S. Pat. No. 5,214,420. A light source 10 is used for generating light energy for illuminating the screen 2. The generated light 9 is further concentrated and directed toward a lens 12 by a mirror 11. Lenses 12, 13 and 14 form a beam columnator operative to columnate light 9 into a column of light 8. A spatial light modulator (SLM) 15 receives data input from a computer 19 via a bus 18 to control the micromirrors of the SLM for selectively reflecting and redirecting portions of light projected from a path 7 toward an enlarger lens 5 and onto a screen 2. FIG. 1B shows a SLM 15 that has a mirror array configured as switchable reflective elements 17, 27, 37, and 47 each includes a mirror 33 supported on a hinge 30 extended from a surface 16 of a substrate as the electromechanical mirror device. When the element 17 is controlled to be in an ON position, a portion of the light from the path 7 is reflected and redirected along a path 6 to lens 5 where it is enlarged or spread along the path 4 to impinge on the screen 2 to form an illuminated pixel 3. When the element 17 is controlled to turn to an OFF position, the light is reflected away from the screen 2 and hence the pixel 3 is dark.
Therefore, the mirror device as shown comprises a plurality of mirror elements to function as spatial light modulator (SLM) and each mirror element comprises a mirror and electrodes. A voltage applied to the electrode(s) generates a coulomb force between the mirror and the electrode(s). The signals applied to the electrodes therefore control and incline the mirror. The mirror element is “deflected” according to a common term used in this specification for describing the operational condition of the mirror element.
When a voltage is applied to the electrode(s) the mirror is deflected the direction of the reflected light is changed in accordance with the deflection angle of the mirror. The present specification refers to an ON state of the mirror when most of the entirety of an incident light is reflected to a projection path designated for image display, and an OFF state when the light reflected to a direction away from the designated projection path for image display.
Further, a state of the mirror is referred to as a specific ratio when the mirror reflects only a portion of an incident light at a specific ratio relative to the ON light to the image projection path. The mirror is operated in this state when shifted between the ON state and the OFF state. And that the light reflected to the projection path with a smaller quantity of light than the state of the ON light is referred to as an “intermediate light”.
The terminology of present specification defines an angle of rotation along a clockwise (CW) direction as a positive (+) angle and that of counterclockwise (CCW) direction as negative (−) angle. A deflection angle is defined as zero degree (0°) when the mirror is in the initial state when there is no voltage applied to the electrode(s).
Most of the conventional image display devices such as the devices disclosed in U.S. Pat. No. 5,214,420 implements a dual-state mirror control that controls the mirrors in a state of either ON or OFF. The quality of an image display is limited due to the limited number of gray scales. Specifically, in a conventional control circuit that applies a PWM (Pulse Width Modulation), the quality of the image is limited by the LSB (least significant bit) or the least pulse width as a control related to the ON or OFF state. Since the mirror is controlled to operate in either the ON or OFF state, the conventional image display apparatus has no way to provide a pulse width for controlling the mirror that is shorter than the control duration allowable on the basis of the LSB. The least quantity of light, which is determined on the basis of the gray scale, is the light reflected during the time duration based on the least pulse width. The limited number of gray scales leads to a degradation of the image.
Specifically, FIG. 1C exemplifies a control circuit for controlling a mirror element according to the disclosure in the U.S. Pat. No. 5,285,407. The control circuit includes a memory cell 32. Various transistors are referred to as “M*” where “*” designates a transistor number and each transistor is an insulated gate field effect transistor. Transistors M5 and M7 are p-channel transistors; while transistors M6, M8, and M9 are n-channel transistors. The capacitances C1 and C2 represent the capacitive loads in the memory cell 32. The memory cell 32 includes an access switch transistor M9 and a latch 32a, which is based on a Static Random Access switch Memory (SRAM) design. The transistor M9 connected to a Row-line receives a data signal via a Bit-line. The memory cell 32 stores data for access is turned on when the transistor M9 receives a ROW signal on a Word-line. The latch 32a consists of two cross-coupled inverters, i.e., M5/M6 and M7/M8, which permit two stable states, that include a state 1 when Node A is high and Node is B low, and a state 2 when Node A is low and Node B is high.
The mirror is driven by a voltage applied to the address electrode abutting an address electrode and is held at a predetermined deflection angle on the address electrode. An elastic “landing chip” is formed at a portion on the address electrode. The address electrode contacts and stops the mirror when the mirror is deflected to a predefined angle. The mirror then deflects toward the opposite direction when a voltage applied to the electrode is switched. The landing chip is designed to have the same potential with the address electrode and that prevents short circuit damages when the address electrode is in contact with the mirror.
Each mirror formed on a device substrate has a square or rectangular shape and each side has a length of 4 to 15 μm. In this configuration, a reflected light spreading outside of an angular ranges specifically designed for image display may inadvertently generated from the gaps between adjacent mirrors. The reflections generated from the gaps between the mirrors have an undesirable effect of degrading the contrast of an image display. As a result, the quality of the image display is adversely affected. In order to overcome such problems, the mirrors are arranged on a semiconductor wafer substrate with a layout to minimize the gaps between the mirrors. A mirror device is generally designed to include an appropriate number of mirror elements wherein each mirror element is manufactured as a deflectable mirror on the substrate for displaying a pixel of an image. The appropriate number of elements for displaying image is in compliance with the display resolution standard according to a VESA Standard defined by Video Electronics Standards Association or television broadcast standards. In the case in which the mirror device has a plurality of mirror elements corresponding to Wide eXtended Graphics Array (WXGA), whose resolution is 1280 by 768, defined by VESA, the pitch between the mirrors of the mirror device is 10 μm and the diagonal length of the mirror array is about 0.6 inches.
The control circuit as illustrated in FIG. 1C controls the mirrors to switch between two states and the control circuit drives the mirror to oscillate to either the ON or OFF deflected angle (or position) as shown in FIG. 1A. The minimum quantity of light controllable to reflect from each mirror element for image display, i.e., the resolution of gray scale of image display for a digitally controlled image display apparatus, is determined by the least length of time that the mirror is controllable to hold at the ON position. The length of time that each mirror is controlled to hold at an ON position is in turn controlled by multiple bit words. FIG. 1D shows the “binary time periods” in the case of controlling an SLM by four-bit words. As shown in FIG. 1D, the time periods have relative values of 1, 2, 4, and 8 that in turn determine the relative quantity of light of each of the four bits, where the “1” is least significant bit (LSB) and the “8” is the most significant bit. According to the Pulse Width Modulation (PWM) control mechanism, the minimum quantity of light that determines the resolution of the gray scale is a brightness controlled by using the “least significant bit” for holding the mirror at an ON position during a shortest controllable length of time.
In a simple example with n-bit word for controlling the gray scale, one frame time is divided into (2n−1) equal time slices. If one frame time is 16.7 msec., each time slice is 16.7/(2n−1) msec.
With the minimum controllable time length set for each pixel in each frame of the image, the quantity of light projected for a pixel is quantified as “0” time slice when a pixel is black with the quantity of light set at zero. The image pixel projected with a “1” time slice is the quantity of light represented by the LSB. The image pixel projected with 15 time slices, in the case of n=4, is the quantity of light represented by the maximum brightness. Based on the above-quantified light, the length of time that the mirror is held at the ON position during one frame period is determined by each pixel. Thus, each pixel controlled by a quantified value greater than “0” time slice, the mirror is held at the ON position according to the number of time slices corresponding to its quantity of light during one frame period. The viewer's eyes integrate the brightness of each pixel as if the image were generated with analog levels of light.
For controlling the deflectable mirror devices, the PWM applies the data formatted into “bit-planes”. Each bit-plane corresponds to a bit weight of the quantity of light. Thus, when the brightness of each pixel is represented by an n-bit value, each frame of data has the n-bit planes. Then, each bit-plane has a “0” or “1” value for each mirror element. According to the PWM control scheme as described in the preceding paragraphs, each bit-plane is independently loaded and the mirror elements are controlled on the basis of bit-plane values corresponding to the value of each bit within one frame. Specifically, the bit-plane according to the LSB of each pixel is displayed as a “1” time slice.
Artifacts are shown between adjacent images pixels when adjacent image pixels are displayed with great differences of quantity of light applying the gray scales having very coarse gray scales. That leads to the degradations of image qualities. The degradations of image qualities are specially pronounced in bright areas of image when there are “bigger gaps” of gray scale, i.e. quantity of light, between adjacent image pixels. The artifacts are caused by a technical limitation that the digitally controlled image display is not controlled by a sufficient number of gray scales, i.e. the levels of the quantity of light. Such problems are particularly caused by the fact that the mirrors are controlled either at the ON or OFF position. The quantity of light of a displayed image is determined by the length of time each mirror is held at the ON position. In order to increase the number of levels of the quantity of light, the switching speed of the ON and OFF positions for the mirror must be increased. Consequently, the digital control signals are required to have a higher number of bits. However, when the switching speed of the mirror deflection is increased, a stronger hinge for supporting the mirror is necessary to sustain a required number of switches of the ON and OFF positions for the mirror deflection. Furthermore, a higher voltage applied to the electrode is required in order to drive the mirrors provided with a strengthened hinge to the ON or OFF position. The higher voltage may exceed twenty volts and may even be as high as thirty volts. The mirrors produced by applying the CMOS technologies probably is not appropriate for operating the mirror at such a high range of voltages, and therefore the DMOS mirror devices may be required. In order to achieve a control of a higher number of gray scales, a more complicated production process and larger device areas are required to produce the DMOS mirror. Conventional mirror are therefore faced with a technical difficulty that in order to produce image display device with smaller size it may be necessary to sacrifice high quality of image display with a higher level of gray scales due to a higher range of the operable voltages.
There are many patents related to the methods and device configurations to control of quantity of light. These patents include the U.S. Pat. Nos. 5,589,852, 6,232,963, 6,592,227, 6,648,476, and 6,819,064. There are further patents and patent applications related to different sorts of light sources include the U.S. Pat. Nos. 5,442,414, 6,036,318 and Application 20030147052. Also, The U.S. Pat. No. 6,746,123 has disclosed particular polarized light sources for preventing the loss of light. However, these patents or patent applications do not provide an effective solution to attain a sufficient number of the gray scales in the digitally controlled image display system.
Furthermore, there are many patents related to a spatial light modulation that includes the U.S. Pat. Nos. 2,025,143, 2,682,010, 2,681,423, 4,087,810, 4,292,732, 4,405,209, 4,454,541, 4,592,628, 4,767,192, 4,842,396, 4,907,862, 5,214,420, 5,287,096, 5,506,597, and 5,489,952. However, these inventions do not provide a direct solution for a person skilled in the art to overcome the above-discussed limitations and difficulties.
In view of the above problems, an invention has disclosed a method for controlling the deflection angle of the mirror to express higher number of gray scales of an image in a US Patent Application 20050190429. In this disclosure, the quantity of light obtained during the oscillation period of the mirror is about 25% to 37% of the quantity of light obtained during the mirror is held on the ON position at all times. According to the improved control schemes, it is no longer necessary to drive the mirror at high speed. Therefore, it is possible to provide a higher number of the gray scale while supporting the mirrors with mirror hinges having a low elastic constant thus reducing the voltages applied to the electrode(s) for controlling the mirrors
The image display apparatuses implemented with the mirror device described above can be broadly categorized into two types, i.e. a single-plate image display apparatus equipped with only one spatial light modulator, and a multi-plate image display apparatus equipped with a plurality of spatial light modulators. In the single-plate image display apparatus, a color image is displayed by periodically changing the colors of light. In a multi-plate the image display apparatus, a color image displayed by applying each of the spatial light modulators to modulate beams of light having different colors and continuously combining and projecting the modulated beams of different colors from each of these light modulators.
Recently, image display apparatuses of higher resolutions such as a full high-definition (Full HD) image display with 1920 by 1080 pixels are required. These requirements demand further design and development improvements of the image display systems in order to satisfy the requirements of a higher resolution display.
A mirror device used in such a display apparatus is generally implemented with a mirror array that includes two- to eight-million mirror-elements arrayed as two-dimensional array on a device substrate. The mirror element of a typical mirror device is a square-shaped mirror with each side having a length of approximately 11 μm. A memory cell for driving the mirror is formed near the mirror element on the substrate. The mirror is controlled by setting the operating voltage of the memory cell, or the drive voltage for deflecting the mirror, to “5” volts or higher to deflect the mirror element supported on an elastic hinge.
A typical mirror device implemented for a full high definition (Full-HD) image display system has micromirrors that have a diagonal size of 24.13 mm (0.95 inches) and a mirror pitch of 11 μm. The micromirrors implemented for a XGA display system has a diagonal size of 17.78 mm (0.7 inches) and a mirror pitch of 14 μm.
FIG. 2 is a diagonal view of a mirror device formed as two-dimensional micromirror array on a device substrate with each of the mirror elements controlled to deflect to different angles thus controlling a reflection direction of incident light.
The mirror device 200 shown in FIG. 2 includes a plurality of mirror elements 300. Each mirror element is supported on an elastic mirror hinge and controlled by a voltage applied to the address electrode (not specifically shown). The mirror elements are configured as two dimensional mirror array on a device substrate 303. FIG. 2 shows a plurality of mirror elements 300 wherein each mirror element includes a square mirror 302 and these mirror elements are configured with equal gaps between adjacent mirrors as two-dimensional array on the device substrate 303. The mirror 302 is controllable by applying a voltage to the address electrode disposed on the device substrate 303. FIG. 2 shows a deflection axis 201 for deflecting the mirror 302 as that indicated by the dotted line. The light emitted from a light source 301 is incident to the mirror 302 along an orthogonal or diagonal direction relative to the deflection axis 201. The distance between the deflection axes 201 between adjacent mirrors 302 is defined as the “pitch” and the distance between adjacent mirrors 302 is defined as the “gap”.
Specific descriptions of mirror operation are provided below by referring to the cross-sectional line II-II of the mirror element 300 of the mirror device 200 shown in FIG. 2. FIGS. 3A and 3B are cross-sectional diagrams of the line II-II indicated in FIG. 2.
The mirror element 300 comprises a mirror 302, an elastic hinge 304 for supporting the mirror 302, two address electrodes 307a and 307b. The address electrodes are placed on two opposite sides across the mirror 302. The mirror element further includes a first memory cell and a second memory cell both for applying a voltage to the address electrodes 307a and 307b in order to control the mirror 302 under a desired deflection state.
The drive circuits for each memory cell are commonly formed in the device substrate 303 to control each memory cell in accordance with the signal of image data. The control signals are applied to modulate the mirror element for controlling the deflection angle of the mirror 302.
FIG. 3A is a cross-sectional diagram of a mirror element 300 controlled to operate in an ON state for reflecting incident light to a projection optical system by deflecting the mirror 300.
When a signal [0, 1] is applied to a memory cell, a voltage “0” (volts; “V”) is applied to the address electrode 307a on one side and a voltage of Va (V) is applied to the address electrode 307b on the other side. As a result, the mirror 302 is drawn by a coulomb force to deflect from the horizontal state toward the direction of the address electrode 307b with a voltage Va (V) applied thereto. This causes the incident light emitted from a light source 301 to reflect to the projection optical system on the mirror 302 (i.e. the ON light state). Note that an insulation layer 306 is coated onto the device electrode 303, and a hinge electrode 305 connected to the elastic hinge 304 is grounded through a via connector (not specifically shown) placed in the insulation layer 306. FIG. 3B is a cross-sectional diagram of a mirror element 300 operated in an OFF state as the incident light is reflected away by deflecting the mirror 302 from the image projection path. When a signal [1, 0] is applied to a memory cell, a voltage Va (V) is applied to the address electrode 307a on one side and a voltage of “0” (V) is applied to the address electrode 307b on the other side. As a result, the mirror 302 is drawn by a coulomb force to deflect from the horizontal position toward the direction of the address electrode 307a with a voltage Va (V) applied thereto. This causes the incident light to reflect away from the image projection light path thus controlling the mirror to operate in an OFF light state.
Incidentally, the Coulomb force generated between the mirror 302 and address electrode 307a, or 307b, is expressed by the following expression:
                              F          =                                    k              ′                        ⁢                                                            eS                  2                                ⁢                                  V                  2                                                            2                ⁢                                  h                  2                                                                    ;                            (        1        )            
where “S” is the area size of the address electrode 307a or 307b, “h” is the distance between the mirror 302 and address electrode 307a or 307b, “e” is the permittivity between the mirror 302 and address electrode 307a or 307b, “V” is the voltage applied to the address electrode 307a or 307b, and “k′” is a correction coefficient.
FIG. 4 is a cross-sectional diagram for showing the optical paths of the incident light projected to a mirror device 200. In the mirror device 200 shown in FIG. 4, each of the mirror elements 300 includes a mirror 302 supported by a hinge 304 juxtaposed on the device substrate 303 contained in a package 308. The package 308 is in the shape of a hollow rectangle with an open top and the top is covered with a cover glass 309 allowing the transmission of light.
The mirror device as described above can usually be produced by applying the production process of a semiconductor device. The production process mainly includes chemical vapor deposition (CVP), photolithography, etching, doping and chemical mechanical polishing (CMP).
In the meantime, attention should be paid to the facts that as the illumination light passes through the gap between the mirrors 302 and projects onto the substrate 303 in the mirror device 200 shown in FIG. 4, electrons flow is generated in a protective layer that is formed on the substrate by using a semiconductor material.
When the electrons move to the semiconductor hinge 304 with a high resistance, changes occur to a charge volume that generates a coulomb force between the mirror 302 and address electrode.
Specifically, a protective layer formed with a multiple-layer structure has a film thickness ranging between 1000- and 2000 angstroms, or between 4000- and 6000 angstroms. In this case, the light of the illumination light in the spectral range of blue to ultraviolet is absorbed in the protective layer. Furthermore, the protective layer also absorbs about 90% of the light with the wavelengths in the infrared region. With The light absorbed in the protective film as described above, the problem is no longer limited to the concerns for the movement of electrons, further considerations must be taken into account about the heat generated when the light projections are absorbed in the protective layer. The heat propagated in the protective film covering over the hinge of the mirror device may also adversely affect the mirror operations due to the effects to the changes to the Coulomb force with the heat propagation changing the operational characteristics of the elastic hinges.
The following lists the patent numbers related to the structures of the conventional mirror devices and the techniques for producing the mirror devices. U.S. Pat. No. 7,183,618: This publication has disclosed a hinge formed in the opening part of a pedestal. U.S. Pat. No. 7,273,693: This publication has disclosed a mirror device comprising a mirror support. U.S. Pat. Nos. 5,673,139; 6,128,121; and 7,068,417. Each of these publications has disclosed a vertical hinge. U.S. Pat. No. 7,022,249: This publication has disclosed a method for forming the root of a hinge. U.S. Pat. No. 5,497,262: This publication has disclosed a horizontal hinge structure.
These patented and published disclosures related to the mirror device and hinge configurations and structures, however do not provide improved methods and device configurations to resolve the above discussed difficulties and limitations.